memory - What is DIMM depth/width?

What is DIMM depth/width?

I think that "(DRAM width) × (the number of DRAMs) = (DIMM width)". I don't know I am right.

In case of the DIMM1 above, what's the values of DIMM depth and width??

Answer

DRAM and DIMM geometry is complex subject, it is better to watch video
https://www.youtube.com/watch?v=ZLCy3pG7Rc0&list=PL5PHm2jkkXmidJOd59REog9jDnPDTG6IJ&index=26&t=0s

I will try to explain it, though.

DRAM chip and its banks

At the lowest level there is a bank: matrix of bits. You can send row address to this bank, and bank reads row and stores it in buffer (also called sense amp). Row is wide, but interface of bank is narrow: only 8 bits in this case.

You then send column number, and banks sets appropriate part of row to the interface.

Col0: you have 0-7 bits.
Col1: you have 8-16 bits

Meanwhile, row is finished, and you move to the next row.

You can think about bank as about storage of many 8-bit width "words". Each block has column and row number.

Your DRAM chip has 64Meg (1024 * 1024 * 64 = 67108864) words, 8 bit each.

8 bit is your DRAM width. 64Meg is depth. Product is called density or capacity.

Think about your DRAM as about home of 67108864 "words" 8 bit each.

So, your chip has 64Megx8=512Mbits capacity (or density)

To make everything even more complex, chip may have many banks. It is still 8 bit width (because all banks have same width) but to address "word" you need bank number, column number and row number.

It could be that your DRAM chip has 2 banks 32Meg depth each. Or 8 banks 8Meg each. I do not know, your spec does not tell me that. Some specs provide number of banks or number of bits in col/row address.

DIMM module: series of DRAM chips

DIMM module consists of several DRAM chips.

You can think about it as about huge DRAM chip which is always 64 bit width. That is because DRAM controller (part of CPU actually) has 64 bit data bus width. That means it reads 64 bits at one time.

DIMM has 8 chips on one side "emulating" 64-bit long chip. And it has 8 chips on the other side. Each side is called rank and could be operated sepately: DRAM controller "enables" (by setting chip select) first rank, reads data, then enables second rank and so on.

Some DIMMs have one rank, but your has two.

DIMM density (capacity) is 512Mbits*16 (because we have 16 chips, 512Mb each) 8Gbits or 1GByte (1024MBytes).

Now, think about DIMM as about 64bit width DRAM. How many 64bit "words" do you have?

You have 128Meg of them. This is your DIMM depth

An illustration: https://www.archive.ece.cmu.edu/~ece740/f11/lib/exe/fetch.php?media=wiki:lectures:onur-740-fall11-lecture25-mainmemory.pdf