Is system tick timer interrupt in SMP system synchronized among CPUs/cores? If not, how is it solved?*
Sorry for my English.
EDIT: With system tick timer interrupt I mean interrupt from system timer that is used by operating system. No CPU frequency clock source.
*I am interested in typical solve of this/similar problem.
Answer
In modern day and age, there are tickless kernels, which do not have static tickrates. They calculate the time until they have to interrupt again and program the APIC (which regulates Interrupts) accordingly.
Windows 10 uses a tickless kernel and the option exists for Linux as well. A tickless kernel increases the throughput of the system (due to less interruptions, less context switches, etc) at the cost of longer response times.
In a tickless environment, every kernel (thus core) takes care about this himself. Synchronizity between cores is not a necessity for a stable environment and the answer to your question simply is:
It depends on the implementation.
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